1/9 december 2001 n high speed: t pd = 5.0 ns (typ.) at v cc =5v n low power dissipation: i cc =4 m a (max.) at t a =25 c n compatible with ttl outputs: v ih =2v (min.) v il = 0.8 (max.) n power down protection on inputs n symmetrical output impedance: |i oh |=i ol = 8 ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 4.5v to 5.5v n pin and function compatible with 74 series 16373 n improved latch-up immunity n low noise: v olp = 0.9v (max.) description the 74vhct16373a is an advanced high-speed cmos 16 bit d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. these 16 bit d-type latches are byte controlled by two latch enable inputs (nle) and two output enable inputs(noe). while the nle input is held at a high level, the nq outputs will follow the data (d) inputs. when the nle is taken low, the nq outputs will be latched at the logic level of d data inputs. when the (noe) input is low, the nq outputs will be in a normal logic state (high or low logic level); when noe is at high level ,the outputs will be in a high impedance state. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v. all inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74vhct16373a 16-bit d-type latch with 3-state outputs non inverting this is preliminary information on a new product now in development are or undergoing evaluation. details subject to change without notice. order codes package tube t & r tssop 74vhct16373attr tssop preliminary data pin connection
74vhct16373a 2/9 input equivalent circuit pin description truth table x : don`t care z : high impedance * : q outputs are latched at the time when the le input is taken low logic level. iec logic symbols pin no symbol name and function 1 1oe 3 state output enable input (active low) 2, 3, 5, 6, 8, 9, 11, 12 1q0 to 1q7 3-state outputs 13, 14, 16, 17, 19, 20, 22, 23 2q0 to 2q7 3-state outputs 24 2oe 3 state output enable input (active low) 25 2le latch enable input 36, 35, 33, 32, 30, 29, 27, 26 2d0 to 2d7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1d0 to 1d7 data inputs 48 1le latch enable input 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage inputs output oe le d q hxx z l l x no change * lhl l lhh h
74vhct16373a 3/9 logic diagram this logic diagram has not to be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied recommended operating conditions 1) v in from 0.8v to 2.0v symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current -20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 75 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 4.5 to 5.5 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 1) (vcc= 5.0 0. 5v) 0 to 20 ns/v
74vhct16373a 4/9 dc specifications ac electrical characteristics (input t r =t f = 3ns) (*) voltage range is 5.0v 0.5v (note 1 : parameter guaranteed by design. t solh =|t plhm -t plhn |, t sohl =|t phlm -t phln | symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 4.5 to 5.5 222v v il low level input voltage 4.5 to 5.5 0.8 0.8 0.8 v v oh high level output voltage 4.5 i o =-50 m a 4.4 4.5 4.4 4.4 v 4.5 i o =-8 ma 3.94 3.8 3.7 v ol low level output voltage 4.5 i o =50 m a 0.0 0.1 0.1 0.1 v 4.5 i o =8 ma 0.36 0.44 0.55 i oz high impedance output leakage current 5.5 v i =v ih or v il v o =v cc or gnd 0.25 2.5 2.5 m a i i input leakage current 0to 5.5 v i = 5.5v or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i =v cc or gnd 44040 m a symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t plh t phl propagation delay time le to qn 5.0 (*) 15 5.0 8.5 1 9.5 1 9.5 ns 5.0 (*) 50 6.0 9.5 1 10.5 1 10.5 t plh t phl propagation delay time dn to qn 5.0 (*) 15 5.5 8.5 1 9.5 1 9.5 ns 5.0 (*) 50 6.2 9.5 1 10.5 1 10.5 t pzl t pzh output enable time 5.0 (*) 15 5.2 9.5 1 10.5 1 10.5 ns 5.0 (*) 50 6.5 10.5 1 11.5 1 11.5 t plz t phz output disable time 5.0 (*) 15 6 10.2 1 11.0 1 11.0 ns 5.0 (**) 50 7 11.2 1 12.0 1 12.0 t w pulse width (le) high 5.0 (*) 555ns t s setup time dn to le high or low 5.0 (*) 444ns t h hold time dn to le high or low 5.0 (*) 111ns t oslh t oshl output to output skew time (note 1) 5.0 (*) 50 1.. 1.5 1.5 ns
74vhct16373a 5/9 capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /n (per latch) dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 5.0v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 5.0v. inputs under test switching: 5.0v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 4101010pf c out output capacitance 6pf c pd power dissipation capacitance (note 1) 5.0 f in = 10mhz 21 pf symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 5.0 c l =50pf 0.6 0.9 v v olv -0.9 -0.6 v ihd dynamic high voltage input (note 1, 3) 5.0 3.5 v v ild dynamic low voltage input (note 1, 3) 5.0 1.5 v
74vhct16373a 6/9 test circuit c l = 15/50 pf or equivalent (includes jig and probe capacitance) r l =r1=1k w or equivalent r t =z out of pulse generator (typically 50 w ) waveform 1 : le to qn propagation delays, le minimum pulse width, dn to le setup and hold times (f=1mhz; 50% duty cycle) test switch t plh ,t phl open t pzl ,t plz v cc t pzh ,t phz gnd
74vhct16373a 7/9 waveform 2: output enable and disable time (f=1mhz; 50% duty cycle) waveform 3 : propagation delay time (f=1mhz; 50% duty cycle)
74vhct16373a 8/9 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.408 0.496 e 7.95 8.25 0.313 0.325 e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0 8 0 8 l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588a
74vhct16373a 9/9 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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